32-Bit Adder and Subtractor Using Multiple Output Domino Logic

Abstract

There is a huge scope for high-speed arithmetic units in VLSI. The proposed technique is for arithmetic operations like adder and subtractor which includes CLA (Carry Look Ahead), Carry Skip Adder techniques with Domino logic and usage of mux for faster computation and reduce the delay and complexity of the architecture.   Cascaded CLA blocks are used here. 8 such structures are used here for faster computation. Mux is also used here for switching between the addition and subtraction operation.   For high-speed performance and low delay, CMOS based domino logic is used here. The proposed design is less complex than other structures and has improved speed during its operation.