Low Power and High-Speed VLSI Architecture for AES Cryptographic Processor

Abstract

This paper shows that a single architecture can be used to build fast and ultra-low-power AES hardware efficiently on FPGA, ASIC, and RISC-V. The system uses automated design exploration and adaptive decision-making to choose architectural parameters like pipeline stages, S-Box implementation, and voltage-frequency scaling based on the workload. A six-class prediction model was developed using TF-IDF, simulating the adaptation of the system during hardware exploration. After five rounds of training, the accuracy increased from 0.44 to 0.458, and the validation loss decreased from 1.227 to 1.199, indicating that the system is still learning. This method can be used for rapid updates and deployment because it takes only 0.045 to 0.07 seconds to complete each epoch.The confusion matrix and a macro-AUC score of 0.784 show that the model consistently distinguishes between good and poor design configurations. Overall, the results demonstrate that the proposed design provides a useful and effective way to guide the development of quick, low-power AES hardware for a variety of platforms.